The present invention relates to a drive apparatus which generates drive signals for driving a liquid crystal display device.
FIG. 1 is an equivalent circuit diagram for a conventional active matrix type liquid crystal display device. Thin film transistors (TFT) 31 and liquid crystal cells 32 are arranged in longitudinal and latitudinal directions to constitute a liquid crystal display surface. Gates of the latitudinally arranged TFT are connected to same scanning electrodes (gate electrodes). Sources of the longitudinally arranged TFT are connected to same signal electrodes (source electrodes). Signal electrodes S.sub.1 -Sn are connected to a data latch circuit 30 which latches a display signal for one scan of video signals on a signal line DS. One electrode of each liquid crystal cell is connected to a drain of a TFT, and other electrode of the cell is connected to a common electrode COM.
FIG. 2 shows voltage wave forms applied individually to the signal electrodes, the common electrode, the scanning electrodes, and the liquid crystal cells. A video signal for one horizontal scanning time 1H on the signal line DS is latched by the data latch circuit 30 so that it is provided from the signal electrodes S.sub.1 -Sn. When the voltage level at the scanning electrodes becomes high, a liquid crystal drive voltage corresponding to the difference between the voltage on the signal electrodes S.sub.1 -Sn, and the voltage on the common electrode COM, is applied to the liquid crystal cells.
During a first field time, the voltage level at gates G.sub.1, G.sub.3 becomes high because of scanning signals (line sequential panel signals corresponding to horizontal synchronizing signals), and the liquid crystal drive voltage is applied to the liquid crystal cells. The voltage at gages G.sub.2, G.sub.4 is then at a low level. Similarly, during a second field time, gates G.sub.2, G.sub.4 sequentially go to a high level condition in accordance with scanning signals, and the liquid crystal drive voltage is applied to the liquid crystal cells. Gates G.sub.1, G.sub.3 are then in a low level condition, and the liquid crystal drive voltage applied during the first field time is retained. In this way, the display device is sequentially driven with polarity inverted in predetermined frame time intervals.
When the liquid crystal display device is driven with polarity inverted in such a way according to a conventional interlaced scanning system, the liquid crystal driving frequency occurring in the case of NTSC-TV (National Television System Committee) signalling amounts to one half of a frame frequency, or 15 Hz. Further, as FIG. 3 shows, an optical response spectrum on the liquid crystal display surface presents a high peak at 15 Hz, thus causing flicker.
In the conventional liquid crystal display unit, it is required that gate signals be sent first to scanning electrodes corresponding to the first field time and then to scanning electrodes corresponding to the second field time. Accordingly, it is necessary to determine, with respect to the display signals latched by the data latch circuit 30, whether they are display signals for the first field time or display signals for the second field time. Therefore, it is necessary to produce field discrimination signals for distinguishing one field time from the other on the basis of horizontal synchronizing signals and vertical synchronizing signals.
According to the existing practice of interlaced scanning, as FIG. 4 shows, scanning, as indicated by solid line, is carried out for each first field time and scanning as indicated by broken line is carried out for each second field time. Scanning for one combined period of a first field time and a second field time defines one frame period.
FIG. 5 shows a wave form of composite video signals for a vertical blanking time during a first field time, and FIG. 6 is a wave form of composite video signals for a vertical blanking time during a second field time. For the convenience of subsequent explanation, individual horizontal scanning times (lines) for composite video signals are numerically designated. It is noted that the following explanation is given on the basis of standard values of NTSC signals. Other standards, such as PAL (Phase Alternation by Line) and SECAM (Sequentiel Couleur a Memoire), will be discussed hereinafter.
A first line of the vertical blanking time portion of the first field time is taken as first, followed by second and third. The vertical blanking time portion of second field time begins from a median point of the 263rd line, and a next first line starts after the 525th line.
In a conventional CRT display, interlaced scanning can be done only by regenerating vertical synchronizing signals and applying a deflecting voltage through a vertical deflection circuit on the basis of the regenerated vertical synchronizing signals, it being not necessary to discriminate the first field time from the second field time through a discrimination circuit provided specially for the purpose. Therefore, field discrimination is carried out in an area such as computer operation with respect to video signals, for which purpose the following technique is employed, for example. As FIG. 7 illustrates, a signal with a duty ratio of about 50% is generated for each individual line. Further, the logic level of the signal relative to a vertical synchronizing signal is detected. This is the level of the signal at the point in time at which the vertical synchronizing signal is generated. It is detected on the basis of which detection a field discrimination signal is outputted. FIGS. 8 and 9 show wave forms of signals for various elements in the FIG. 7 block diagram during the respective vertical blanking time portions of first field time and second field time.
In such conventional field discrimination, it is necessary to generate signals of exactly 50% in duty ratio. For this purpose that high frequency signals, that are several times to several tens of time as high as the frequency of a horizontal synchronizing signal are required. This naturally necessitates a larger and more complex circuit.
Now, in a liquid crystal display device, scanning is switched over between first field time and second field time on the basis of a field discrimination signal. Therefore, if an erroneous field discrimination signal is issued, an abnormal operation may occur such that an image for only one field is displayed, or no image is displayed, on the liquid crystal display screen. In order to prevent such trouble, therefore the usual practice has been to provide a circuit for correcting such abnormal operation if an abnormal field discrimination signal is provided from the field discrimination unit. FIG. 10 is a circuit diagram schematically showing a conventional field discrimination unit which provides field discriminating signals for discriminating one field from the other, of a first field time and a second field time with respect to video signals of above-mentioned interlaced scanning type, on the basis of a composite synchronizing signal added to each video signal.
In FIG. 10, as shown by 35, is a synchronizing signal generating circuit which receives composite synchronizing signals added to video signals and generates a low level synchronizing signal RES for each leading point of time of each frame. It also generates high level synchronizing signals CK for each first field time and each second field time. Shown by 36 is a discriminating signal output circuit which receives the synchronizing signals RES and CK from the synchronizing signal generating circuit 35 and outputs field discriminating signals FP. This circuit consists of a D-flip-flop circuit.
The synchronizing signal RES provided by the synchronizing signal generating circuit 35 is transmitted as a reset signal to the D-flip-flop circuit, while the synchronizing signal CK is given as a clock signal. An inverted output terminal O of the D-flip-flop circuit is connected to a data input terminal D and a field discriminating signal FP is provided from the inverted output terminal O.
FIG. 11 is a timing chart illustrating the operation of the field discriminating unit.
FIG. 12 shows relative phases of synchronizing signals RES and CK, in which the synchronizing signals RES and CK are identical in pulse length. Further, they are overlapping in relation, synchronizing signals CK are caused to lag a slight period of time .DELTA.t behind synchronizing signals RES. As can be seen from FIG. 11, a synchronizing signal CK is generated with a lag of time .DELTA.t relative to the leading end of a frame (the front end of second field time). Similarly, at the leading end of a first field time, at which it does not overlap a synchronizing signal, a synchronizing signal is generated with a lag of time .DELTA.t relative to the leading end.
In the field discriminating unit, when synchronizing signal RES is transmitted as a reset signal to a reset input terminal R of the discriminating signal output circuit 36 at the leading point of time of a frame, the output of the inverted input terminal O, or field discriminating signal FP, shifts to a high level state and such output condition is kept as it is. It is not influenced by a synchronizing signal to be given as a clock signal with a time lag of .DELTA.t.
Subsequently, when synchronizing signal CK is transmitted to the discriminating signal output circuit 36 at the leading part of the first field time, the field discriminating signal FP is inverted from high level to low level in synchronism with the generation of the synchronizing signal CK. Then, at the leading point of time of a next following frame, when the synchronizing signal RES is transmitted to the discriminating signal output circuit 36, the frame discriminating signal FP is inverted from a low level to a high level. In this way, the field discriminating signal FP shifts to a high level during the second field time and to a low level during the first field time, such a cycle of operation is repeated.
The above described manner of operation represents the case where no error is involved in video signals. However, where a video tape is used as a source of signals for trick regeneration or where video signals involve considerable noise, or where the device is connected to a video signal source of an interlaced (field fixed), errors may often occur in video signalling. Thus, signals for one field only are continually provided as field discriminatinn signals, or signals are provided with which field discrimination is totally impossible.
In any such case, there is no change in field discrimination signals FP between the first field time and the second field time. Therefore, display for one field only is made in regenerating devices, such as liquid crystal display device. When a liquid crystal display device, in particular, is to be driven, it is particularly necessary to drive a liquid crystal layer by ac power. Therefore, unless voltage is applied to scanning lines corresponding to one of the field, the corresponding portion is disabled to display. Thus, display performance of the device is noticeably degraded or the device becomes totally inoperable.
FIGS. 13A through 13D are timing charts showing normal operation of the field discriminating unit in comparision with various aspects of possible misfunction. FIG. 13A illustrates a normal pattern of operation, while FIGS. 13B to 13D show cases of misfunction by way of example.
FIG. 13B shows an instance in which there has been no generation of a synchronizing signal RES for some period of time. Thus, the level of the field discriminating signal FP is inverted, instead of that of the synchronizing signal RES, each time synchronizing signal CK is generated. In this case, the field discriminating signal FP is inverted periodically, though not accurately, and therefore the trouble involved is relatively insignificant.
FIG. 13C shows a phenomenon which may occur when operation returns from a malfunctional condition to normal condition, in which case output timing for synchronizing signal RES delays one field time. In such a case, identical field discriminating signals FP are successively generated for some periods of time. However, this is merely a temporary phenomenon and is therefore of minor nature.
On the other hand, FIG. 13D represents a case in which synchronizing signals RES are continuously provided for consecutive one-field periods, in which case field discriminating signals FP are continually kept at constant level. This poses a serious problem as stated above.